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1. RISCV_multicore_cache_controller RISCV_multicore_cache_controller Public

   This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.

   SystemVerilog 4 2

2. UVM-Verification-of-CNN-hardware-accelerator UVM-Verification-of-CNN-hardware-accelerator Public

   Project used for BSc thesis

   SystemVerilog 3

3. Fault-Tolerant-FIR-projekat Fault-Tolerant-FIR-projekat Public

   Pair-and-a-Spare active redundancy technique was used on FIR filter in order to make this system more robust on permanent faults. (Projekat iz predmeta "Digitalni sistemi otporni na greške", master…

   VHDL 2

4. Pacman-projekat Pacman-projekat Public

   Sequential and parallel implementation of Pacman game. ( Drugi zadatak iz predmeta "Multiprocesorski sistemi", master akademske studije )

   C++ 1

5. Fox-and-Geese-Android-projekat Fox-and-Geese-Android-projekat Public

   Multiplayer Fox And Geese Android Game . ( Treci zadatak iz predmeta "Razvoj softvera za embeded operativne sisteme", master akademske studije)

   Java 1

6. Merge-sort Merge-sort Public

   Sequential and parallel implementation of Merge sort algorithm. ( Prvi zadatak iz predmeta "Multiprocesorski sistemi", master akademske studije)

   C 1