RISC-V

@risc_v

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.

riscv.org
Joined July 2014
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  1. Retweeted
    Apr 17

    The 1.9 release introduces extended co-simulation support with . See the on /VexRiscv demo with a verilated UART connected to Renode via 's brand new Wishbone support, with interrupt-driven input:

    12 retweets 12 likes
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  2. Retweeted
    Apr 17

    is a global revolution, and it's great to see the EU funding a great team to build systems based on RISC-V:

    1 reply 6 retweets 21 likes
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  3. Retweeted
    Apr 20

    🚀 The project will introduce a & platform for future development within space % aeronautical applications based around ISA. This novel technology made-in-Europe will be employed in space and aviation domains 👉

    , and
    10 retweets 16 likes
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  4. Retweeted
    Apr 20

    We are a week away from our webinar on formal verification. Join us on 27 April, 5 pm BST, to learn how we can help you speed up your RISC-V verification with fast, exhaustive proofs and corner case bug hunting.

    4 retweets 1 like
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  5. Retweeted
    21 hours ago

    Codasip co-hosts a RISC-V meetup in Israel tomorrow. Meet us virtually and learn how to deploy a RISC-V core in a risk-free way😉 -Yafo via

    4 retweets 9 likes
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  6. 14 hours ago

    Did you miss the Bay Area meetup? Be sure to watch the recording to learn from , and about the latest support and next steps for cache coherent memory fabric based on :

    1 retweet 5 likes
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  7. Apr 21

    At the virtual Linley Spring Processor Conference, presented on their new vector extensions for the ISA. Find out what at had to say about ’ presentations here:

    3 retweets 12 likes
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  8. Retweeted
    Apr 14

    Congratulations to as our newest Ambassador! Thank you so much for your ongoing leadership and collaboration.

    3 retweets 7 likes
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  9. Retweeted
    Apr 15

    Linux 5.6 Brings New Features for

    11 retweets 15 likes
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  10. Retweeted
    Apr 15

    , , and InCore Semiconductor are cooking up a completely open source hardware security module that uses a CPU. Check it out! Talk to us!

    1 reply 4 retweets 7 likes
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  11. Retweeted
    Apr 15

    (中) 2020 RISC-V CON Seires: Andes Custom Extension™ – Accelerating Domain-Specific Architecture | YiChiang Chang, Andes Technology (Chinese)

    3 retweets 3 likes
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  12. Retweeted
    Apr 14

    We just released a new video on the impact of the revolution. Watch several of our members, including , , , , , , Syntacore and explain how they use :

    11 retweets 15 likes
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  13. Retweeted
    Apr 11

    Yay Linux boots up on my RISC-V emulator written in Rust! It's compiled to WASM so you can run Linux on your browser.

    1 reply 51 retweets 112 likes
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  14. Retweeted
    Apr 15

    Check out the Bay Area RISC-V Group Meetup: Cache Coherent Memory Fabric based on RISC-V! Taking place tomorrow, April 16th at 6PM PDT / 9PM EDT Register ➡️

    2 retweets 10 likes
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  15. Retweeted
    Apr 15

    Join us for the 2nd meetup in Israel, hosted by us, and , to talk RISC-V debug & trace infrastructure, unique paging techniques & SweRV Core. The online event is on Thursday, April 23rd, 2020, 6:00pm-7:30pm Israel Day Time.

    9 retweets 12 likes
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  16. Apr 17

    .’s latest blog post highlights how to overcome challenges associated with making open-source deployment effective. Learn more here:

    6 retweets 7 likes
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  17. Apr 17

    The preliminary round of the National Undergraduate Integrated Circuit Innovation and Entrepreneurship competition-RISC-V Challenge Cup is coming up in June! Find out more details from :

    2 retweets 5 likes
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  18. Retweeted
    Apr 16

    The Bay Area Group Meetup, Cache Coherent Memory Fabric based on RISC-V, is starting soon! Head over and register to attend this free virtual meetup! ⏰ Tonight, April 16th at 6PM PDT / 9PM EDT ➡️

    6 retweets 17 likes
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  19. Apr 16

    . kicked off its online event today. Be sure to tune in tomorrow at 1:10 p.m. JST for a presentation on a processor with an inter-chiplet wireless communication interface for shape-changeable computers. Click here for more info:

    1 like
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  20. Retweeted
    Apr 12

    New RISC-V Service Tools Virtual Meetup Details here:

    1 retweet 3 likes
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