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Technology Summary - IEEE 1149

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Application Information

The JTAG / Boundary scan portal

� Treat the JTAG clock (TCK) and associated mode signal (TMS) like any other critical net on your design for layout purposes. For optimal performance, specify these as short nets and use a standard (R-C network) clock termination.�

� Make the signals easily accessible. If using a test fixture then conveniently placed test points can be used to access the JTAG signals via a b-o-n (bed of nails) fixture. If testing on the bench then specify the most robust header you can (repetitive connects and disconnects can weaken flimsy cable assemblies). Further tip - shrewd design may enable you to access the JTAG header or test points via vent holes

in a boxed design for simple 'closed-case' reconfiguration of a design.

� Add JTAG Technologies' AutoWrite� signal to your header to speed in-system programming of flash memory devices.

� Always check BSDL models for compliance warnings during schematic entry. Some few devices require special conditions to be present on pins for them to become JTAG-valid or compliant to the IEEE 1149.1 boundary-scan standard. Such conditions are typically specified as COMPLIANCE CONFORMANCE or DESIGN WARNINGS within the BSDL .

IEEE 1149 Application Information

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Diagram shows suggested termination on input signals. Use of buffer and multiple TCK/TMS signals assists with fan-out.