RSS FeedsNews
- Audiocast: Filling EDA's innovation gaps 6/7/2007
One on One with Magma's Rajeev Madhavan - SOC design and CPU design begin to converge 6/7/2007
Ever since the emergence of RTL and cell-based synthesis, the teams that design high-end microprocessors have worked differently than the teams that design SOCs. That's been an industry axiom. But it may be an axiom on its way into history. - Panelists predict EDA and semiconductor challenges of 2017 6/6/2007
DAC: EDA executives make conservative 10-year predictions, but touch on Moore's Law, multicore trends, the need for system-level design, and more. - Large chipmakers still developing EDA tools 6/6/2007
DAC: The overall number of vendors developing in-house EDA tools may be down, but large companies like IBM and Freescale still see homegrown EDA software as a necessity and a competitive advantage. - Audiocast: TSMC's Kuo Wu discusses the chip ecosystem 6/6/2007
Kuo Wu, deputy director of TSMC's product and design services marketing division, sounds off on the state of the EDA market.
In-Depth
- Taking a bite out of power: techniques for low-power-ASIC
design 5/24/2007
Even if you are designing an ASIC or SOC that doesn’t target a low-power application, you need to become familiar with low-power-design techniques, because the newest generation of silicon-process technologies inherently leaks power. - Compact imaging systems face partitioning issues 5/24/2007
CMOS imagers enable many choices, from cameras on chips to distributed-processing architectures, but the wild card may be autofocus technology. - Squeezing a low-cost multiprocessor platform out of 130 nm 4/26/2007
LSI’s Zevio project shows that success in consumer electronics does not always mean implementing the fastest SOC in the latest and greatest process technology. - A methodology for front-end power predictability 4/18/2007
Power closure is a primary concern for IC designers today. But a successful power closure flow needs to begin before logic synthesis and needs to account for power's relationship to timing and signal integrity. - Efficient simulation and validation for mixed-signal SOCs 3/29/2007
Adding analog content to digital-IC designs can be a nightmare. Simulation and validation tools can help ward off the terror.
Experts
- DAC stumbles looking to find firm future 6/6/2007
Another lackluster conference highlights the challenges EDA companies face. - Thread or die: EDA must lead, or get out of the way of Moore’s Law 5/21/2007
The most important opportunity and challenge for EDA is to stay ahead of design requirements, and software has to scale at the same rate as the designs themselves to keep pace, writes Isadore Katz of CLK Design Automation. - Delivering advanced SystemVerilog verification capabilities to design teams 5/16/2007
Some say you need to be a full-fledged verification expert or specialist with experience using the latest object-oriented languages to tap into the productivity benefits of advanced verification techniques but Takahiro Kobayakawa from Fujitsu Kyushu Network argues otherwise. - What to expect at 45-nm 5/11/2007
Getting IC design right the first time takes on new urgency as costs escalate; tighter partnerships form earlier in the process to defray costs and tackle complexity. - The verification plan from hell 4/18/2007
Akiva Michelson, CTO of Ace Verification, explains how under-emphasizing verification planning can truly undermine your most critical projects.
DesignIdeas
- Use SystemVerilog for coverage metrics 3/29/2007
SystemVerilog constructs suit RTL design, high-level modeling, testbench creation, and assertion specification.
