Research

The differential fact that makes Navarre AsyncArt a research group different from the rest from which work with PLDs is its vocation of being a pioneer in the field of asynchronous electronic circuits implementation. This type of technology is based on the elimination of the omnipresent digital systems clock and for years the most important research groups of the sector at international level (like those of SUN, Philips, Caltech, Intel or Sharp among others) have been working in the development of asynchronous systems convinced that through them it happens the future of the digital electronics.

The research of which Navarre AsyncArt is born has its origin in the first works developed five years ago by J.D. Garcia Lasheras, works that were based on the substitution of the digital clock by different intelligent devices and that were recognized with the Society of the Information Special Prize in the XIV Young Researchers National Contest (Spain, 2001). Since then this investigation has gone evolved until crystallizing, thanks to the support of the research group on Communicactions, Signals and Microwaves of the Public University of Navarre, in the first organization at world-wide level able to offer a commercial methodology of asynchronous systems implementation optimized for FPGAs: the N-Protocol.

Of between the advantages from which our design team can benefit when using this asynchronous methodology instead of the conventional one, they emphasize a greater performance, a smaller power consumption and a greatly reduced electromagnetic interference (EMI). Thanks to this, Navarre AsyncArt not only can offer electronic designs for portable devices equipping them with a greater autonomy, but also that our upper performance developments are able to fulfill all the electromagnetic compatibility normatives (EMC).  

The main lines in which our research group works at the present time are the following ones:

• N-Protocol:  direct inheritance of the first Garcia Lasheras'works, N-Protocol bases its operation on the progressive decomposition of digital systems into self-timed blocks. Each one of these blocks has an intelligent synchronizer and a series of communication channels through which it  shares the information with adjacent blocks. The adoption of which technically it's known as Bounded-Time approach allows version 2.0 of N-Protocol to be integrated in different conventional EDA tools.

• Bardenas/EVO project: Inspired by Transport Triggered Architecture (TTA) concept for processors design, the Bardenas/EVO project is aimed to the development of an asynchronous evolutionary soft-processor for FPGAs. Based in real-time reconfiguration, the proposed architecture is made up of a central nucleus from which different functional units grow and are destroyed depending on the activity that the processor is carrying out. With the results obtained until the moment, our forecasts point out that the first Bardenas/EVO commercial version will be operative in first half of 2007.

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